module hand_split #(
	parameter CHANNEL = 2
)(
	input  clk,
	input  rst_n,
	
	input  in_valid,
	output in_ready,
	
	output [CHANNEL -1:0]out_valid,
	input  [CHANNEL -1:0]out_ready
);

//in out hand_en
wire 			   in_hand_en  = in_valid  & in_ready;
wire [CHANNEL -1:0]out_hand_en = out_valid & out_ready;

//history hand record
reg  [CHANNEL -1:0]history_q;
wire [CHANNEL -1:0]history_d;
wire 			   history_en;

assign history_en = (|out_hand_en) || in_hand_en;
assign history_d  = in_hand_en ? {CHANNEL{1'b0}} : history_q | (out_valid & out_ready);
always @(posedge clk or negedge rst_n)begin
	if(~rst_n)  		history_q <= {CHANNEL{1'b0}};
	else if(history_en) history_q <= history_d;
end

//out valid
assign out_valid = {CHANNEL{in_valid}} & (~history_q);

//in_ready
assign in_ready  =  ((history_q | out_ready) == {CHANNEL{1'b1}});

endmodule
